1. Field of the Invention
The disclosed subject matter relates generally to the fabrication of semiconductor devices and, more particularly, to methods for providing variable feature widths in a self-aligned spacer-mask patterning process.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors as defined by the critical dimension (CD) of the gate electrode, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. Existing optical lithography is capable of high-throughput processing, but the patterning pitch of a single optical lithography step is limited. A challenge for lithography is to devise tools, materials and processes that can reliably, efficiently and quickly pattern structures with smaller dimensions, reduced pitch or varied pitches.
The CD of the gate electrodes, which also defines the channel length, is typically limited by the photolithography processes employed. To improve the reliability of the patterning process, a large number of evenly spaced lines are typically formed in a regular pattern. The width of each line and the pitch between lines is determined by the patterning process. In an exemplary self-aligned technique, referred to as self-aligned double patterning (SADP), a hard mask layer is formed above a gate electrode material layer and a plurality of mandrel line elements is formed above the hard mask layer. Spacers are formed on sidewalls of the mandrel and the mandrel is removed, leaving the spacers as an etch mask for patterning the hard mask layer. The pitch of the spacers is effectively double that of the mandrel elements. Another technique, referred to as self-aligned quadruple patterning (SAQP), forms another set of spacers and removes the first set, effectively quadrupling the pitch of the mandrel elements. The patterned hard mask layer is used to etch the underlying gate electrode material layer.
In some devices, arrays of narrow gate electrodes are bounded by wider lines of gate electrode material to provide mechanical stability to the pattern for various processing steps, such as planarization and cleaning. Due to the regular nature of the spacers and the self-aligned process, it is inherently difficult to pattern lines with widths greater than the characteristic width of the patterning process, referred to as the 1× width. The patterning of wider lines, such as those needed for high current capacity power rails, typically requires additional masking and patterning steps, giving rise to increased fabrication complexity and cost. Due to the use of multiple patterning technologies, defects may also increase, such as overlay errors, pitch walking, hard mask profile defects, etc.
The present application is directed to eliminating or reducing the effects of one or more of the problems identified above.